1. Field of the Invention
The present invention generally relates to a digital image processing apparatus and, more specifically, to a digital image processing apparatus arithmetically processing original image data for effecting image data converting process such as gradation correction, sharpening of image quality, and other processes such as feature extraction from original image data.
2. Description of the Prior Art
A digital image processing apparatus comprises hardware such as an image input circuit for inputting image data, an image output circuit for outputting image data, an image memory for storing image data, a processing circuit for arithmetically processing image data, and so on; a host CPU controlling such hardware and arithmetically processing image data by means of software; and so on. In some cases, a control circuit for high speed hardware control, which can not be provided by the software processing by the host CPU, is included.
The arithmetic operation comprises processing of the image data provided from the image input circuit or of the data read from the image memory carried out by a processing circuit, and processing carried out on the data on the image memory by the host CPU by means of software. The hardware processing employing the processing circuit is preferred for high speed processing. In that case, the image input circuit and the processing circuit, or the image memory and the processing circuit must be coupled with each other in one way or another so as to enable exchange of image data. When the hardware structure is limited, the coupling can be implemented by prescribed signal lines. When the structure of the hardware must have flexibility and capability of being extended, the coupling employing data buses is necessary. Especially, in a general purpose image processing apparatus having various arithmetic functions to be utilized for many purposes, a data bus for exclusive use is provided in general to transfer image date between each of the circuits of the hardware.
FIG. 1 shows a structure of a conventional image processing apparatus in which portions of the hardware are coupled with each other by data buses exclusively used for image data. As is shown in the figure, the image processing apparatus comprises a host CPU 1, an image input circuit 2, an image output circuit 3, an image memory M1, a processing circuit P1, a host CPU bus B0 and an image date bus B1. The number of the image input circuit 2, image output circuit 3, image memory M1 and of the processing circuit P1 may be two or more if necessary.
The input of the image data is effected by transferring image data from the image input circuit 2 to the image memory M1 through the image data bus B1.
The image data read out from the image memory M1 are inputted to the processing circuit P1 through the image data bus B1 to be arithmetically processed, and the resulting image data are again written in the image memory M1 through the image data bus B1, thus the arithmetic processing of the image data is completed.
The output of the image data is effected such that the image data read from the image memory M1 are outputted to external image display apparatus, image recording apparatus and the like through the image data bus B1 and the image output circuit 3.
The image data obtained from the image input circuit 2 can be directly brought to the processing circuit P1 and the data outputted from the processing circuit P1 can be directly brought to the image output circuit 3 dependent on the internal structure of the image data bus B1. In this manner, the operating states such as image input, image processing, image output are determined by the connection between each of the circuits through the image data bus B1.
In the foregoing, whether the image data to be handled is multiple-valued image data (or gray data) having a plurality of bits of information per 1 pixel or binary image data having 1 bit of information per 1 pixel was not taken in consideration. In general, in image data processing, multiple-valued images and binary images are often handled together: for example, there are such cases where a first inputted multiple image data is binary converted, with the binary image being processed; multiple valued image data are processed using a binary data as a control data. Therefore, each of the circuits in FIG. 1 and the image data bus B1 must treat both the binary image and the multiple-valued image. They must have the bit width at least corresponding to the gradation of the multiple-valued image to be handled.
Conventionally, when a binary image is handled in such image processing apparatus, for example, when the processing circuit P1 generates a binary image as a result of processing and the data is stored in the image memory Ml, the binary image is expanded to a multiple-valued image to be stored in the image memory M1 for multiple-valued images. In order to expand a binary image to a multiple-valued image, "1" and "0" are changed to be in correspondence with respective bits of a multiple-valued image. When a pixel of the multiple-valued image is represented by 8 bits, "1" and "0" of the binary image are respectively expanded to 255 (1,1,1,1,1,1,1,1) and 0 (0,0,0,0,0,0,0,0). By expanding in this way, the arithmetic operation on binary image can be carried out in the processing circuit P1 for multiple-valued images to provide appropriate result. By employing values corresponding to a white level and black level in the multiple-valued image as the specified two values, the binary image data can be directly displayed on a circuit for displaying multiple-valued images.
As an example of the treatment of binary images in the image processing apparatus, the binary image is used as control data for switching arithmetic functions of the processing circuit P1. For example, in a maximum value evaluating operation in which two planes of image data are compared with each other to determine larger value at each pixel position, subtraction operation is carried out for every pixel between two planes of multiple-valued images, a binary image is provided which corresponds to a borrow data generated at that time, and two planes of multiple-valued images are switched from each other on pixel by pixel basis to be synthesized using the binary image.
FIG. 2 shows a processing circuit P1 capable of switching arithmetic functions by means of a binary image and the connection of the processing circuit P1 and the peripheral circuits proposed prior to the present invention. In the figure, a binary image memory Mp is provided attendant on the processing circuit P1 for storing data of binary images outputted from the processing circuit P1. Function registers FRa and FRb are provided for designating arithmetic function of the processing circuit Pl. A function selector FS is provided for switching the values of two function registers FRa and FRb in accordance with read data from the binary image memory Mp to apply the same to a function input FI of the processing circuit P1. Image data buses B1a and B1b are provided for supplying image data to two image data input ports IPa and IPb. An image data bus B1c is provided for supplying the result of processing outputted from the processing circuit P1 to other circuits.
In the above described maximum value evaluating process, the data of two planes of images are inputted to the processing circuit P1 through data buses B1a and B1b in the first frame. A function code designating subtraction processing is set in both function registers FRa and FRb. The processing circuit P1 carries out the subtraction processing regardless of the state of the function selector FS. A binary image output terminal 02 of the processing circuit P1 is separately set such that borrow data generated by the subtraction processing is outputted therefrom, and a binary image corresponding to the borrow data of each pixel is stored in the binary image memory Mp. In the second frame, a function code for directly outputting the image data inputted to the input ports IPa and IPb is set in the function registers FRa and FRb. The function selector FS switches functions to apply the same to the processing circuit P1 based on the borrow data outputted for each pixel from the binary image memory Mp. Data of two planes of images are inputted to the processing circuit P1 from the data buses B1a and B1b as in the first frame, and data of two planes of images are switched between each other in accordance with the switching of the function to be outputted from the multiple-valued image output terminal O1 as the result of processing. Since the switching of the function is carried out based on the borrow data dependent on magnitude of two planes of image data, the maximum value evaluated image output can be obtained as the result of processing. By changing the setting of the function code, the minimum value output can also be provided.
In the foregoing, description was given of the handling of binary images in a conventional image processing apparatus with reference to FIGS. 1 and 2. The conventional method for treating binary images mainly comprises the following three disadvantages.
(1) Disadvantages derived from the use of a circuit originally designed for multiple-valued images for binary images by expanding the binary image to the multiple-valued image when a binary image is handled as the result of processing or as the data to be processed. First, it is uneconomical, because a number of multiple-valued image memory having unnecessary large capacitances must be provided when a number of image memories are required for binary images. It is difficult to implement arithmetic functions characteristic of binary images effectively in hardware since the binary images are handled in the same bit widths as multiple-valued images in the processing circuit. In addition, the number of data bus can not be freely increased since the width of the whole data bus becomes large, when a number of binary images should be handled simultaneously.
(2) Disadvantages derived from attendant arrangement of the binary image memory for switching arithmetic function of the processing circuit on the processing circuit. First, it is uneconomical when processing circuits of the same type are to be increased in accordance with the object of processing since binary image memories are arranged no matter whether they are needed or not. It is difficult to increase the number of binary image memories, since the binary image memory is attendant on the processing circuit. It is difficult to control a processing circuit by using binary image generated in another processing circuit, and it is difficult to carry out arithmetic operation between binary image memories belonging to different processing circuits, since the relation between the processing circuit and the binary image memory is fixedly determined.
(3) Disadvantages derived from different handling of binary images. Binary images resulting from the processing and binary images to be processed are expanded to multiple-valued images and the data bus B1 and the image memory M1 are used for processing. The binary image used for switching arithmetic function of the processing circuit P1 is processed by using the binary image memory Mp arranged attendant on the processing circuit P1. The handling of binary image is troublesome, since the binary images are sometimes expanded to the multiple-valued images and sometimes not, and the portions for handling binary images are different case by case, as described above. The characteristics of the binary images are not always fixed, and there is a request, for example, for arithmetic operation on binary images on the binary image memory Mp. The conventional apparatus is not suitable for flexible handling of binary images.